• Design
  • Italy
  • Cernusco Lombardone


The candidate will join the PCB Layout Team in the EWS-Final test areas (ATE semiconductors), based on the testing platform required by the customer (mainly Teradyne, Advantest, Credence, Verigy, Agilent). The incumbent will be responsible for carrying out the layout design, ensuring testability, quality and manufacturability. Knowledge of semiconductor testing technologies is appreciated.



  • Design the Layout of PCB multilayers High density;
  • Draw up the electrical schematics;
  • Provide technical support in order to meet customer requirements;
  • Generate of gerber files, technical and assembly documentation;
  • Carry out feasibility and pre-layout analysis, double check, implementation of work requirements and layout rules.


  • Degree in electronic engineering or diploma in electronics.
  • Excellent aptitude for detail and order.
  • Interest in working towards objectives and as part of a team.
  •  Knowledge of PCB Layout, preferably with software: Mentor Graphics Expedition Enterprise,
  • Cadence Allegro PCB Design, Cadence Allegro Package Design.
  • Good knowledge of High density multilayer PCB layout, including Power, RF, Analog and High speed digital circuits.
  • Knowledge of layout rules (IPC), Footprint and Library Management.
  • Good knowledge of the English language
  • Knowledge of signal and power integrity, strong interpersonal skills, ability to work in international teams complete the profile

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