MEMS T1 fine pitch probe card supports wafer testing for logic and SOC devices. This proprietary MEMS technology is suitable for multi DUT testing and small die size requirements.

MEMS T1 features:
·    Fine pitch down to 55 µm in line
·    Reduced contact force for probing over active area and reduced scrub area
·    Easy probe replacement
·    Flexible PAD layout on multiple line and corner PAD


 

ROUTE60™  supports fine pitch and high current requirements on logic and SOC devices. The unique probe design guarantees robust and excellent performance even in extreme conditions such as fine pitch, high current and high temperature.

ROUTE60™ features:
·    Fine pitch down to 78 µm in line
·    High current capability (550 mA)
·    Reduced contact force for probing over active area and reduced scrub area
·    Easy probe replacement
·    High temperature testing (up to 175°C)
 

Bumptek technology is suitable for area-array probing and peripheral PAD layout both on bump and pre-bump (aluminium) PAD application.

BUMPTEK  features:
·    Pitch down to 150 µm in array configuration (130 µm peripheral)
·    Pin count up to 9000 pins
·    Multi-die probing
·    Easy probe replacement
·    Dedicated organic interconnection technology to reduce cost and lead time
     compared to MLC solution
 

This vertical technology supports wafer testing for logic and memory (NAND-NOR) devices.
This solution provides excellent reliability and quality for multi-DUT testing.

ROUTE99™ features:
·    Pitch down to 110 µm in line
·    Multi-DUT probing and large array probing up to 1 TD on 12” wafer
·    Dedicated SUPERFLAT® PCB technology for strict planarity on large array
     probing and superior signal and power integrity
·    Easy probe replacement
·    Cost savings compared to traditional mems-based cards for memory
     applications
 

Cantilever technology supports wafer testing for fine pitch on logic devices. Our cantilever technology has been upgraded year-by-year achieving impressive capability on complex design and low pad damage requirements

Cantilever technology includes:
·    Fine pitch down to 40 µm in line (20/40 staggered)
·    Special short beam and coax cable options for high speed testing
·    “Helium” technology, a dedicated and proprietary cantilever design for low
     force and minimized scrub area, 50% reduction compared to traditional
     cantilever solutions.